Quantum computers are getting faster and more capable, but a new benchmark across machines from Google, IBM and Quantinuum puts a sharp number on how far current hardware remains from the circuits envisioned for some of the field’s major computational targets. The benchmark, called the quantum universal operation performance system, or QUOPS, measures the largest random quantum circuits a processor can execute with a specified level of reliability, while also accounting for how quickly the machine can perform them. Applied directly to physical qubits, it gave Google’s Willow a score of 216, IBM’s ibm boston 204, Quantinuum’s H2-1 1,320 and Helios-1 1,504. The researchers then used resource estimates for two prospective applications, factoring RSA-2048 and simulating the FeMoco molecule, to estimate QUOPS requirements of roughly 250 million and 340 million, respectively.
Quantum computers are usually characterized by quantities such as physical qubit counts and individual gate error rates. Those measurements are useful for understanding hardware components, but they do not directly say how large a complete computation a machine can execute successfully.
QUOPS was designed to make that system-level capability measurable across different quantum architectures.
The benchmark uses randomized circuits built from alternating layers of two types of operations. One layer applies CNOT gates between randomly paired qubits. The other applies independently randomized single-qubit rotations around the X, Y or Z axes. The width of a circuit, w, is its number of qubits. Its size, s, counts single-qubit rotations plus twice the number of CNOT gates.
That construction deliberately separates width from size. A processor might be able to handle a relatively wide circuit that is not very deep, or a deep circuit involving fewer qubits. QUOPS therefore maps a two-dimensional capability region rather than reducing everything immediately to a single number.
The benchmark’s standard success threshold is a mean process polarization of at least 1/√e, about 61 percent. Process polarization measures how closely the noisy implementation of a compiled circuit matches the intended quantum operation. The threshold is a convention rather than a physical boundary, but it gives the benchmark a fixed definition of successful execution.
The scalar QUOPS score is then the largest successful circuit size within an admissible region defined by
w² ≤ s ≤ w³.
This excludes very narrow, very deep circuits and very wide, shallow circuits from the single-number score. The authors chose the region because it encompasses circuit shapes expected to be relevant to early quantum utility while retaining a connection to square-circuit benchmarks such as quantum volume.
The benchmark also reports a QUOPS rate. Unlike a raw gate-per-second figure, this rate is reduced when errors require additional samples to recover useful information. For error mitigation, the relevant sampling overhead is approximately 1/α² when the circuit polarization is α.
Four very different machines on the same test
The researchers applied QUOPS directly to physical qubits on four processors available in 2026.
Google’s Willow is a 105-qubit superconducting processor with degree-4 connectivity. IBM’s ibm boston is a 156-qubit superconducting processor with degree-3 connectivity. Quantinuum’s H2-1 has 56 trapped-ion qubits, while Helios-1 has 98. The two trapped-ion systems provide all-to-all connectivity through ion transport.
The differences between the machines are reflected strongly in their measured rates as well as their scores.
Willow reached a QUOPS score of 216 at a rate of 2.0 × 10⁷ QUOPS per second. IBM’s processor reached 204 at 3.1 × 10⁵ QUOPS per second. H2-1 reached 1,320 at 353 QUOPS per second, while Helios-1 reached 1,504 at 303 QUOPS per second.
The benchmark does not simply reward a machine for having more physical qubits. Connectivity, compilation, error rates, circuit execution time and other architectural details all affect the capability region.
For the physical-qubit experiments, the researchers compiled the random benchmark circuits to each processor’s native operations and used mirror circuits to estimate their process polarization. Mirror-circuit fidelity estimation allows the researchers to characterize circuits that are difficult to simulate directly on a classical computer.
The statistical procedure was designed to avoid declaring a circuit successful simply because a finite experimental sample happened to produce a favorable estimate. QUOPS scores are required to have at least 95 percent confidence, while the estimated capability regions carry a 90 percent confidence requirement.
Leakage detection pushes the trapped-ion scores higher
Helios-1 and H2-1 provided another way to examine the benchmark because some errors can be detected rather than merely inferred.
On these trapped-ion processors, population can leak out of the computational qubit states. The researchers used leakage-detection procedures that identify affected executions so those shots can be discarded.
For Helios-1, leakage postselection raised the measured score from 1,504 to 1,824 QUOPS. The corresponding rate at the higher score was 247 QUOPS per second, compared with 344 QUOPS per second at the 1,504-QUOPS point.
For H2-1, postselection increased the score from 1,320 to 1,392. The rate at 1,320 QUOPS rose from 353 to 360 QUOPS per second, while the rate at 1,392 QUOPS was 231 QUOPS per second.
These results illustrate why the benchmark reports both capability and throughput. Discarding erroneous executions can allow larger circuits to meet a fidelity threshold, but the discarded work reduces the effective rate.
Allowing much more error changes the reachable circuit size
The researchers also examined what the machines could do if much lower circuit polarizations were accepted as potentially useful through error mitigation.
They considered a polarization threshold of 1 percent. Under the benchmark’s sampling model, that corresponds to an overhead of approximately 10,000 circuit executions.
At that threshold, the experimentally measured and extrapolated regions gave error-mitigated scores of 651 QUOPS for Willow, 899 for ibm boston, 7,796 for H2-1 and 20,442 for Helios-1.
The associated rates were dramatically lower: about 1.2 × 10⁴ QUOPS per second for Willow, 91 QUOPS per second for ibm boston, 0.09 QUOPS per second for H2-1 and 0.29 QUOPS per second for Helios-1.
The larger scores therefore do not mean the machines can execute those circuits with the same reliability as their standard QUOPS scores. They represent circuits whose lower polarization could, under the assumed error-mitigation model, be compensated for with substantially more samples.
Some of these 1 percent results are extrapolations rather than direct measurements. The extrapolation assumes that, at fixed width, mean circuit polarization decreases exponentially with circuit size. The authors explicitly describe that assumption as heuristic because the compilation freedom allowed by QUOPS means existing theoretical results about exponential decay for random circuits do not directly establish that behavior for these compiled benchmark circuits.
They caution that extrapolated capability regions do not have the same evidentiary weight as directly measured regions.
Google and IBM show a different balance of speed and depth
The detailed experiments on Willow and ibm boston illustrate how QUOPS separates circuit size from execution speed.
For Willow, simulations using a noise model supplied through Cirq predicted a maximum standard QUOPS score of 144 at a circuit shape of width 6 and size 144. The simulated QUOPS rate was 7.69 × 10⁶ QUOPS per second.
The same simulation extended the capability region to a predicted error-mitigated score of 512 at width 8 and size 512, with an estimated rate of 8.42 × 10⁵ QUOPS per second at that point.
The experimental search instead identified a maximizing circuit shape of width 6 and size 216, and a subsequent rate experiment at that shape used 500,000 shots per benchmark circuit. That experiment achieved the same QUOPS score while optimizing the amount of data collected to maximize throughput.
IBM’s simulated ibm boston processor reached a predicted standard score of 204 at width 6 and size 204, with an estimated rate of 5.72 × 10⁵ QUOPS per second. Its simulated error-mitigated region extended to 1,344 QUOPS at width 12, but with a much larger estimated overhead of 3,629 and a rate of about 2.08 × 10³ QUOPS per second.
The experimental IBM rate calculation required an approximation because circuits of different shapes were interleaved in the jobs, making precise shape-specific execution times unavailable. The researchers therefore estimated the rate from batch-level timing and then scaled it by the measured process polarization.
The benchmark was also run on encoded logical qubits
The most direct demonstration of QUOPS beyond physical qubits came from Helios-1.
The researchers encoded up to eight logical qubits using the distance-three J7,1,3K Steane code and ran the benchmark on those encoded qubits. The logical circuits were compiled into Clifford+T operations, with Clifford gates implemented transversally and T gates supplied through prepared magic states.
The resulting fully fault-tolerant implementation achieved a score of 40 QUOPS at a width of four logical qubits, at a rate of 4.9 QUOPS per second.
That score is much smaller than Helios-1’s physical-qubit score of 1,504. The difference is a direct illustration of the overhead introduced by fault-tolerant encoding and error correction in this particular implementation.
At the 40-QUOPS point, the mirrored circuits contained an average of 20 CNOT gates and 20 T gates. The distribution of T counts varied from circuit to circuit because the randomized benchmark circuits require different synthesized rotations and because some state-preparation procedures use repeat-until-success operations.
The researchers synthesized each arbitrary-angle rotation to three bits of angular precision. At width four and size 40, this synthesis alone would leave a process polarization of about 77.3 percent in the absence of other noise. Increasing the synthesis precision to four bits would reduce synthesis error but increase the number of logical operations, while two-bit precision would introduce substantially more synthesis error.
The choice therefore represented a balance between synthesis error and the remaining logical error budget.
Three versions of the logical processor
The 40-QUOPS result came after three successive implementations of the Steane-code experiment.
The first version reached 24 QUOPS. The second incorporated improved magic-state preparation, more parallel processing and per-shot randomization and reached 40 QUOPS. The third changed the error-correction strategy so that the complete encoded circuit was fault tolerant under composition of its individual gadgets.
In the first two versions, individual logical components were fault tolerant, but the way those components were combined could allow a single physical fault to propagate into an uncorrectable logical error at some circuit locations.
The third implementation used classical Pauli-frame tracking and correlated decoding to prevent that problem. The researchers also developed a stricter fault-tolerant state-preparation procedure and merged portions of error correction with magic-state injection where possible.
Parallel preparation of multiple magic states further reduced execution time.
The experiments therefore produced two different improvements. The QUOPS score increased from 24 to 40, while the rate increased from 1.3 to 4.9 QUOPS per second.
Simulations of the logical circuits were consistent with the fully fault-tolerant implementation having logical error rates that scale approximately as the square of the physical error rate over the range tested. The optimized earlier implementation departed from that scaling at sufficiently low physical error rates.
The researchers emphasize that the 40-QUOPS logical result does not saturate Helios-1’s potential fault-tolerant capability. They identify higher-rate codes, improved magic states and alternative direct fault-tolerant implementations of non-Clifford gates as approaches that could increase capability, although those possibilities were not demonstrated by this benchmark itself.
What utility-scale circuits would require
The authors then used QUOPS to put resource estimates for two proposed quantum computations onto the same scale as the hardware measurements.
For RSA-2048 factoring, they used a published resource estimate requiring 1,399 logical data qubits and about 6.5 × 10⁹ Toffoli gates over an expected 9.2 executions. One execution takes about 12 hours in that estimate.
For FeMoco, a quantum chemistry calculation using a 76-orbital active space, they used an estimate requiring 1,459 logical qubits and 9.99 × 10⁸ Toffoli gates for a single phase-estimation run.
To compare these Toffoli-heavy computations with the RP(θ)- and CNOT-based QUOPS circuits, the researchers converted Toffoli gates into an estimated T-gate resource. They used four T gates per Toffoli, reflecting the assumption that many Toffoli operations in these algorithms occur in compute-uncompute pairs.
They then asked what T-gate error rate would allow the entire algorithm to reach the same 1/√e polarization threshold used by QUOPS. The resulting logical T-gate error rates were about 1.8 × 10⁻¹⁰ for RSA-2048 and 1.3 × 10⁻¹⁰ for FeMoco.
The analysis also accounted for the finite precision needed to synthesize the arbitrary-angle rotations in QUOPS. The optimum in the model occurred at about 22 T gates per synthesized rotation for both problems.
That resource matching produced QUOPS targets of approximately 2.5 × 10⁸ for RSA-2048 and 3.4 × 10⁸ for FeMoco.
The corresponding target rates, using the assumed execution times, were about 5.7 × 10³ QUOPS per second for RSA-2048 and 8.0 × 10² QUOPS per second for FeMoco.
The comparison with current machines is stark. The directly measured physical-qubit scores are in the hundreds or low thousands, while the modeled challenge-problem targets are in the hundreds of millions.
The authors describe the present gap as roughly five orders of magnitude in QUOPS score.
The targets are not direct measurements of what a future machine must achieve. They depend on assumptions including the Toffoli-to-T conversion, neglect of Clifford errors, a particular rotation-synthesis model, and the treatment of stochastic errors. The paper notes that changing the assumed Toffoli-to-T conversion can shift the targets by roughly a factor of two.
Fault tolerance changes the scaling
The researchers used two hypothetical families of fault-tolerant machines to examine how that gap might be crossed.
The first family is based on rotated surface-code patches arranged on a two-dimensional degree-4 lattice. The modeled machines contain between 5,000 and 50,000 physical qubits and assume a uniform physical gate error rate of 0.1 percent.
Under the model, the 5,000-qubit machine reaches about 1,950 QUOPS, the 10,000-qubit machine 9,240, the 25,000-qubit machine 68,470 and the 50,000-qubit machine 273,632.
The calculations use the FLASQ resource model to estimate logical timesteps, spacetime resources and magic-state consumption. They also divide the available error budget among logical Clifford errors, T-state errors and rotation-synthesis errors.
As the hypothetical systems become larger, the limiting factor can change. At higher widths, the available physical qubits constrain the code distance and therefore the number of logical qubits that can be supported. At lower widths, increasingly accurate non-Clifford resources become important. The authors note that the magic-state cultivation model used in these projections eventually imposes a floor on the logical error rate.
The second family assumes all-to-all physical connectivity and considers either surface-code or concatenated symplectic-double-code logical architectures. The model uses 1,000 to 10,000 physical qubits, a two-qubit error rate of 10⁻⁴ and single-qubit and memory error rates of 10⁻⁵.
For 10,000 physical qubits, the modeled fully connected architecture reaches a QUOPS score of about 2.2 million.
These projections are not experimental results. They rely on detailed architectural assumptions, resource-estimation models and fitted approximations. The authors use them to illustrate how fault tolerance could alter the scaling of computational capability rather than to establish what a particular future machine will achieve.
The measured logical machine is slower for a reason
The experimental Steane-code result and the projections point to a distinction that is central to the benchmark.
Fault-tolerant encoding adds substantial overhead because logical operations require error correction, ancilla states and, for non-Clifford operations, magic-state preparation and injection.
In the demonstrated experiment, that overhead leaves the logical processor far below Helios-1’s physical-qubit QUOPS score.
But the projected fault-tolerant systems behave differently as the number of physical qubits grows. In the authors’ models, increasing the size of a fault-tolerant machine can increase the number of logical qubits and the tolerable circuit size rather than simply adding more physical operations to the same unprotected computation.
For the degree-4 surface-code architecture, the projections reach 273,632 QUOPS with 50,000 physical qubits. The fully connected architecture reaches 2.2 million in the 10,000-physical-qubit case.
Even those projected capabilities remain below the estimated 250 million to 340 million QUOPS targets for the two challenge problems.
The authors therefore conclude from their models that the remaining gap would require some combination of lower physical error rates, more physical qubits or more efficient logical architectures.
Historical estimates show a different trajectory
The paper also uses historical quantum-volume results to estimate approximate QUOPS scores for IBM and Quantinuum processors dating back to 2018.
These historical values are not direct QUOPS measurements. For IBM, the researchers matched compiled CNOT counts between quantum-volume and QUOPS circuits. For Quantinuum, they inferred an effective two-qubit gate fidelity from the heavy-output probabilities reported in quantum-volume experiments and then converted that into an estimated QUOPS score.
The resulting values are intended to reveal broad trends rather than provide precise historical comparisons.
For IBM, the estimated scores rise from about 22 QUOPS for the 2018 Tokyo result to about 302 for the 2025 Heron r3 result. For Quantinuum, the estimates rise from about 55 for an early H0 result to about 1,456 for H2-2 data from September 2025.
Adding the direct 2026 measurements, the fitted trend lines correspond to approximate doubling times of 2.1 years for IBM and 1.4 years for Quantinuum.
The paper stresses that individual historical estimates should be treated as approximate, with expected accuracy within roughly a factor of two. The quantum-volume conversion assumes a global depolarizing model, treats two-qubit gates as the dominant error source and uses platform-specific conversion assumptions.
QUOPS is intended to follow the hardware as it changes
The benchmark’s central purpose is not simply to assign today’s machines a number. Its construction allows the same basic capability measurement to be applied as processors move from physical qubits to encoded logical qubits and as their architectures change.
That flexibility comes partly from allowing the benchmark circuits to be compiled into architecture-specific gate sets. The same high-level randomized circuit can therefore be tested on a superconducting processor, a trapped-ion machine or a fault-tolerant logical architecture.
The approach also makes compilation part of the measured computational capability. Routing, gate synthesis, ancilla use and other compilation costs can all affect the polarization of the resulting circuit.
The benchmark is not intended to reproduce the detailed structure of every quantum algorithm. Its circuits are dense, randomized and deliberately disordered. The authors argue that this makes them difficult to compile and therefore provides a conservative proxy for computational capability, while acknowledging that real algorithms have different structures.
The method has its own assumptions as well. The foundational definition assumes a factorized noise model that does not fully capture effects such as leakage or some forms of non-Markovian noise. The operational benchmark is designed to remain usable when those assumptions fail, but the interpretation of its estimators depends on the conditions under which the mirror-circuit methods remain reliable.
The researchers also note that the standard QUOPS score is tied to an arbitrarily chosen 1/√e threshold. Error-mitigated scores require assumptions about sampling overhead, and extrapolated regions require an additional assumption about exponential polarization decay.
For the challenge-problem comparisons, still more assumptions enter. The conversions simplify the algorithms to their dominant non-Clifford resources and neglect some error sources and architectural details.
Those qualifications are important because the paper’s central numerical comparison combines direct experimental measurements with modeled targets and projections. The measured QUOPS scores do not themselves demonstrate that any of the modeled future architectures will achieve their projected performance.
The experimental results instead establish a common measurement framework in which physical and logical quantum processors can be tested through the size, reliability and throughput of the circuits they execute.
The study was posted on the arXiv preprint server.
